Semiconductor memory device production method

ABSTRACT

In a semiconductor memory device production method for a semiconductor memory device having a capacitor formed by a high dielectric insulation film and a noble metal upper electrode successively formed on a noble metal lower electrode, the formation of the capacitor is followed by anneal in a gas mixture atmosphere of oxygen concentration of 0 to 5% and nitrogen at temperature of 300 to 400 degrees C. This enables to reduce the leak current at room temperature and suppress leak current increase during a high temperature operation.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a production method forproducing a semiconductor memory device having a high dielectric thinfilm capacitor.

[0003] 2. Description of the Related Art

[0004] As the semiconductor memory device integration becomes higher,the area where a capacitor can be formed becomes smaller. It has becomedifficult to obtain a desired area for the capacitor. To cope with this,there has been suggested to use a highly dielectric substance such asBST and PZT for a dielectric film, whereas a study has been made on ahighly dielectric thin film capacity using a noble metal as the upperand lower electrodes.

[0005] Now, explanation will be given on an example of production methodof the highly dielectric thin film capacitor. Firstly, a MOSFET isformed by a known method on a Si substrate, and an insulation film ofSiO₂ is formed by the CVD method or the like. Then, a capacitancecontact plug is formed from polysilicon on the aforementioned insulationfilm. After this, a barrier layer of Tin/Ti and a noble metal lowerelectrode of Ru or the like are formed and processed into a desiredshape by RIE. Then, by using the electron cyclotron resonance(ECR)-MOCVD method, a thin film of (Ba, Sr)TiO₃ (BST) is formed at thesubstrate temperature of 200 degrees C. After this, in order to get ridof peeling of the lower electrode, the BST thin film is crystallizedwith the RTA processing at 700 degrees C in nitrogen. Next, a noblemetal upper electrode using Ru or the like is formed to obtain a thinfilm capacitor. Then, with a known procedure, surface treatment isperformed including formation of a passivation film.

[0006] In the highly dielectric thin film capacitor thus obtained, theBST thin film is formed at a low temperature of 200 degrees C beforecrystallized by the RTA processing. Accordingly, the crystallization ofthe boundary between the lower electrode and the BST thin film is notsufficient. Moreover, formation of the upper electrode causes a damageto the boundary between the lower electrode and the BST thin film andcrystallization of this boundary is also insufficient.

[0007] Although the leak current at room temperature is preferably inthe order of 10⁻⁸ (A/cm²) when ±1V is applied, the leak current during ahigh temperature operation becomes as high as 10⁻⁷ (A/cm²) when ±1V isapplied. FIG. 6 shows the relationship between the voltage applied andthe leak current density at the temperature of 25 degrees C and 80degrees C.

[0008] Accordingly, in a highly integrated semiconductor device using asa capacitor a BST film which is one of the highly dielectric films, thecapacitor need to be annealed so as to assure a sufficientcrystallization of the dielectric film and a stable leak currentcharacteristic.

[0009] However, when anneal is performed in an atmosphere containingoxygen so as to obtain a sufficient crystallization of the dielectricfilm and stable leak current characteristic, if the anneal temperatureis high, there arises a problem of conductivity defect and peeling-offat the contact portion under the lower electrode.

[0010] Consequently, it is preferable to perform anneal at a lowtemperature. Japanese Patent Publication 10-233485 discloses aninvention in which oxygen or hydrogen plasma treatment is performed toeliminate dielectric film defects and impurities of a dielectric objectsurface and after this, post-anneal is performed at the temperatureequal to or below 750 degrees C. Even if the plasma treatment isperformed, the 750 degrees C is not a low temperature and there arises aproblem of peel-off and conductivity defect. Moreover, the plasmatreatment increases the number of production steps.

[0011] Moreover, in order to lower the anneal temperature, JapanesePatent Publication 10-189908 discloses an invention in which thecrystallized BST is formed by sputter of 550 degrees C and a metal oxidefilm is formed before post-anneal is performed in an oxygen atmosphereof 2 to 10 atmospheric pressure, for example, at a temperature of 500degrees C. However, even if the anneal is performed at 500 degrees C,there arise the problems of peel-off and conductivity defects.

SUMMARY OF THE INVENTION

[0012] It is therefore an object of the present invention to provide asemiconductor memory device production method in which a low temperatureanneal is performed so as to reduce a leak current at room temperatureand suppress leak current increase during an operation at a hightemperature.

[0013] The present invention provides a semiconductor memory deviceproduction method for a semiconductor memory device having a capacitorformed by a high dielectric insulation film and a noble metal upperelectrode which are successively layered on a noble metal lowerelectrode, the method being characterized in that the formation of thecapacitor is followed by anneal in a nitrogen atmosphere of 1atmospheric pressure at temperature of 300 to 400 degrees C.

[0014] According to another aspect of the present invention, there isprovided a semiconductor memory device production method for asemiconductor memory device having a capacitor formed by a highdielectric insulation film and a noble metal upper electrode which aresuccessively layered on a noble metal lower electrode, the method beingcharacterized in that the formation of the capacitor is followed byanneal in a gas mixture atmosphere of oxygen concentration of 5% orbelow and nitrogen under 1 atmospheric pressure at temperature of 300 to400 degrees C.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a cross sectional view of a semiconductor memory deviceaccording to the present invention.

[0016]FIG. 2 is a schematic cross sectional view showing a semiconductormemory device production method according to the present invention.

[0017]FIG. 3 is a schematic cross sectional view showing a semiconductormemory device production method according to the present invention.

[0018]FIG. 4 is a graph showing the relationship between a voltageapplied and a leak current density at room temperature in thesemiconductor memory device according to the present invention.

[0019]FIG. 5 is a graph showing the relationship between a voltageapplied and a leak current density in the semiconductor memory deviceaccording to the present invention at temperature of 25 degrees C and 80degrees C.

[0020]FIG. 6 is a graph showing the relationship between a voltageapplied and a leak current density in a conventional semiconductormemory device at temperature of 25 degrees C and 80 degrees C.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Description will now be directed to embodiments of the presentinvention with reference to the attached drawings.

[0022]FIG. 1 is a cross sectional view of a semiconductor memory deviceaccording to the present invention. The semiconductor memory deviceaccording to the present invention uses a (Ba, Sr)TiO₃ (BST) film as acapacity insulation film, and a noble metal such as Ru for the capacityupper electrode and the lower electrode, and includes: P type siliconsubstrate 12; MOSFET 14 provided on the silicon substrate 12 in an areaisolated from the other MSOFETs by an element isolation insulation film13; an inter-layer insulation film 16 such as Sio₂ for covering theMOSFET 14; a capacity contact 18 formed in a connection hole through theinter-layer film 16; and a capacitor 20 provided on the capacity contact18 via a silicon contact layer 24 and a silicon diffusion resistantconductive layer 26.

[0023] The MOSFET 14 includes a gate electrode 34 formed on a gate oxidefilm 36, and a source/drain region made from an n-type diffused layer 33formed at the both sides of the gate electrode 34 in the siliconsubstrate 12.

[0024] The capacitance contact 18 is formed from polysilicon.

[0025] The silicon contact layer 24 is provided to reduce a contactelectric resistance between the polycilicon forming the capacitancecontact 18 and the silicon diffusion resistant conductive layer 26. Thesilicon contact layer 24 is formed from, for example, a TiSi₂ film.

[0026] The silicon diffusion resistant conductive layer 26 is providedto prevent generation of a metal silicide by the metal constituting thelower electrode and the polysilicon of the capacitance contact 18, andis made from a high melting point metal such as a TiN layer and a WNlayer or their nitride.

[0027] The capacitor 20 includes a lower electrode 28, a capacitanceinsulation film 30 formed by a dielectric film formed on the lowerelectrode 28, and an upper electrode 32. The lower electrode 28 and theupper electrode 32 are formed by a noble metal film such as Ru, Ir, andPt.

[0028] The capacitance insulation film 30 is formed by a high dielectricfilm such as a (Ba, Sr)TiO₃ film (BST).

[0029] The capacitor 20 is connected to the n-type diffused layer 33 ofMOSFET 14 via the capacitance contact 18.

[0030] Hereinafter, explanation will be given on a semiconductor memorydevice production method using a high dielectric thin film capacitoraccording to a first embodiment of the present invention with referenceto FIG. 2 and FIG. 3. FIG. 2 and FIG. 3 are cross sectional viewsshowing semiconductor memory apparatus production steps according to thepresent invention.

[0031] Firstly, according to a known method, a MOSFET (not depicted) isprepared by forming a gate oxide film, a gate electrode, and n-typediffused layer at both sides of the gate electrode in an area isolatedby an element separation insulation film. Furthermore, by a knownmethod, SiO₂ inter-layer film 16 having a film thickness of 300 nm isformed using the CVD method or the like. Next, a connection hole 17 isformed through the interlayer insulation film 16.

[0032] Subsequently, as shown in FIG. 2(a), a polylsilicon layer 19 islayered on the inter-layer insulation film 16 using the CVD method andphosphorus (P) using ion implantation method to lower the resistance ofthe polysilicon layer 19.

[0033] Next, as shown in FIG. 2(b), the polysilicon layer 19 is etchedback so as to expose the inter-layer insulation film 16 and form apolysilicon plug 21 in the connection hole 17.

[0034] Next, as shown in FIG. 2(c), the sputter method or the like isused to form a silicon diffusion resistant conductive layer 26 includinga Ti layer 22 having a film thickness of 30 nm and a TiN layer having afilm thickness of 50 nm on the inter-layer insulation film 16 and thepolysilicon plug 21.

[0035] Next, RTA treatment is performed in a nitrogen atmosphere tochange the Ti layer 22 into a TiSi layer so as to form a silicon contactlayer 24 of the TiSi layer as shown in FIG. 2(d) on the insulation filmlayer 16 and the polysilicon plug 21.

[0036] Next, as shown in FIG. 3(e), the CVD sputter or the like is usedto form a 100 nm lower electrode layer 28 from Ru or the like on thesilicon diffusion resistant conductive layer 26.

[0037] Next, the plasma etching is performed using a gas mixture ofoxygen and chlorine, as shown in FIG. 3(f), to process the lowerelectrode 28, the silicon diffusion resistant conductive layer 26, andthe silicon contact layer 24 into desired shapes.

[0038] Next, as shown in FIG. 3(g), a 20 nm BST film is formed as acapacitance insulation film 30 by the ECRCVD method using Ba(DPM)₂,Sr(DOM)₂, Ti(i-OC₃H₇)₄, and oxygen gas as raw materials.

[0039] Next, as shown in FIG. 3(h), 100 nm upper electrode layer 32 isformed on the BST film, from Ru or the like by the DC sputter method,thus preparing a high dielectric thin film capacitor.

[0040] After forming the high dielectric thin film capacitor, anneal isperformed for about 40 minutes under a normal pressure in a nitrogenatmosphere at temperature of 300 to 400 degrees C.

[0041] Thus, the semiconductor memory device according to the presentinvention is ready.

[0042]FIG. 4 shows the relationship between the voltage applied (voltageof the upper electrode to the lower capacitance electrode) and the leakcurrent density at room temperature in the semiconductor memory deviceusing the high dielectric thin film capacitor thus obtained according tothe present invention. As is clear from FIG. 4, the leak current issignificantly reduced when anneal has been performed under a normalpressure in a nitrogen atmosphere at the range of 400 degrees C.

[0043] Moreover, FIG. 5 shows the relationship between the voltageapplied and the leak current density at temperature of 25 degrees C and80 degrees C. According to FIG. 5, even at temperature of 80 degrees C,±1V voltage applied assures 10⁻⁸ (A/cm²). That is, it can be seen thatthe leak current increase at a high temperature operation is suppressed.

[0044] Description will now be directed to a semiconductor memory deviceproduction method according to a second embodiment of the presentinvention. The method according to the second embodiment is identical tothe method of the first embodiment up to the formation of the highdielectric thin film capacitor. In the second embodiment, after the highdielectric thin film capacitor is formed, anneal is performed in a gasmixture of oxygen (5% or below) and nitrogen at temperature of 300 to400 degrees C for about 40 minutes.

[0045] Addition of oxygen to nitrogen can eliminate oxygen deficiencyimmediately after the BST film formation. In addition to the preferablecrystallization by nitrogen anneal, oxygen deficiency can be compensatedby oxygen, which suppresses the leak current.

[0046] Almost identical leak results were obtained with the oxygenconcentration of 0 to 5%. No effect was obtained at 200 degrees C.

[0047] When anneal is performed in a gas mixture atmosphere of oxygenconcentration above 5% (10%, 20%, 50%, 100%) and nitrogen in thetemperature range of 300 to 400 degrees C, if TiN is used for thesilicon diffusion resistant conductive layer, TiN reacts with oxygen andnitrogen is removed, causing peel off.

TiN+O₂→TiO₂+½N₂↑

[0048] Moreover, TiO₂ is an insulating material, damaging conductivityto disable function as a circuit.

[0049] It should be noted that Japanese Patent Publication 10-189908discloses a method in which crystallized BST is formed by sputtering at550 degrees C and a metal oxide film is formed before performingpost-anneal in an oxygen atmosphere of 2 to 10 atmospheric pressurehigher than 1 atmospheric pressure, at the temperature of, for example,500 degrees C. However, anneal in a 100% oxygen atmosphere at thetemperature of 500 degrees C causes peel off regardless of the pressureand there arises a problem of non-conductivity.

[0050] Moreover, as has been described above, in the second embodiment,after the upper electrode is formed, anneal is performed in a mixtureatmosphere of oxygen concentration of 0 to 5% and nitrogen. This isbecause, when sputtering is used for formation of Ru on the BST thinfilm, defects may be involved on the boundary between the BST and Ru,and this can be recovered by annealing after formation of the upperelectrode. That is, if the upper electrode is formed by CVD, no defectis caused in the BST thin film and it is possible to perform anneal,after formation of the BST thin film, in a mixture atmosphere of oxygenconcentration of 0 to 5% and nitrogen.

[0051] Moreover, in the explanation of the first and the secondembodiment, an example of (Ba, Sr)TiO₃ is used as the capacitanceinsulation film. However, it is also possible to use a Pb(Zr, Ti)O₃ filmin this invention.

[0052] Moreover, in the explanation of the aforementioned embodiments,the upper and the lower electrode is formed from Ru, for example.However, it is also possible to use a noble metal such as Pt or Ir forthe upper and the lower electrode so as to obtain the same effects.

[0053] Moreover, in the explanation of the aforementioned embodiments,the capacitor is a box type stack capacitor in which the lower electrodeis processed into a parallelopiped. However, the present invention isnot to be limited to that capacitor configuration if the high dielectriccapacitance insulation film is sandwiched by the upper and the lowerelectrode.

[0054] As has been described above, according to the present invention,after formation of the capacitor, anneal is performed in a gas mixtureatmosphere of oxygen concentration 0 to 5% and nitrogen at thetemperature of 300 to 400 degrees C, which causes rearrangement of theboundary between the electrode and the BST thin film to improve thecrystallization of the boundary between the electrode and the BST thinfilm. This reduces the leak current at room temperature and suppressesthe leak current increase during high temperature operation. Even at 80degrees C, it is possible to assure the order of 10⁻⁸ (A/cm²) with the±1V voltage applied.

[0055] The invention may be embodied in other specific forms withoutdeparting from the spirit or essential characteristic thereof. Thepresent embodiments are therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims rather than by the foregoingdescription and all changes which come within the meaning and range ofequivalency of the claims are therefore intended to be embraced therein.

[0056] The entire disclosure of Japanese Patent Application No.11-113206 (Filed on Apr. 21, 1999) including specification, claims,drawings and summary are incorporated herein by reference in itsentirety.

What is claimed is:
 1. A semiconductor memory device production methodfor a semiconductor memory device having a capacitor formed by a highdielectric insulation film and a noble metal upper electrode which aresuccessively layered on a noble metal lower electrode, the method beingcharacterized in that the formation of the capacitor is followed byanneal in a nitrogen atmosphere of 1 atmospheric pressure at temperatureof 300 to 400 degrees C.
 2. A semiconductor memory device productionmethod for a semiconductor memory device having a capacitor formed by ahigh dielectric insulation film and a noble metal upper electrode whichare successively layered on a noble metal lower electrode, the methodbeing characterized in that the formation of the capacitor is followedby anneal in a gas mixture atmosphere of oxygen concentration of 5% orbelow and nitrogen under 1 atmospheric pressure at temperature of 300 to400 degrees C.
 3. A semiconductor memory device production method asclaimed in claim 1, wherein if the noble metal upper electrode is formedby the CVD method, the anneal is performed after formation of the highdielectric insulation film.
 4. A semiconductor memory device productionmethod as claimed in claim 2, wherein if the noble metal upper electrodeis formed by the CVD method, the anneal is performed after formation ofthe high dielectric insulation film.
 5. A semiconductor memory deviceproduction method as claimed in claim 1, wherein the high dielectricinsulation film is a (Ba, Sr)TiO₃ film or Pb(Zr, Ti)O₃ film.
 6. Asemiconductor memory device production method as claimed in claim 2,wherein the high dielectric insulation film is a (Ba, Sr)TiO₃ film orPb(Zr, Ti)O₃ film.
 7. A semiconductor memory device production method asclaimed in claim 1, wherein the noble metal is Ru, Ir, or Pt.
 8. Asemiconductor memory device production method as claimed in claim 2,wherein the noble metal is Ru, Ir, or Pt.
 9. A semiconductor memorydevice production method as claimed in claim 1, wherein the capacitor isformed by: a step of processing the noble metal lower electrode into adesired shape by RIE treatment; a step of forming a high dielectricinsulation film at the substrate temperature of 200 degrees C by usingthe CVD method; a step of crystallizing the high dielectric insulationfilm by the RTA treatment of 700 degrees C in nitrogen; and a step offorming the noble metal upper electrode.
 10. A semiconductor memorydevice production method as claimed in claim 2, wherein the capacitor isformed by: a step of processing the noble metal lower electrode into adesired shape by RIE treatment; a step of forming a high dielectricinsulation film at the substrate temperature of 200 degrees C by usingthe CVD method; a step of crystallizing the high dielectric insulationfilm by the RTA treatment of 700 degrees C in nitrogen; and a step offorming the noble metal upper electrode.